1. Field of the Invention
The present invention relates to a method for producing a semiconductor device comprising at least one semiconductor element and an isolation region which are formed in an epitaxial layer formed on a semiconductor substrate. More particularly, the present invention relates to a method for forming both a silicon oxide layer which lies on and around the semiconductor element, and an isolation region which lies around the semiconductor element and has an opposite conductivity type to that of the epitaxial layer.
2. Description of the Prior Art
In a case where a semiconductor integrated circuit is produced by forming semiconductor elements, such as transistors, and passive elements, such as diffused resistors, in an epitaxial layer formed on a silicon semiconductor substrate, generally, after a silicon oxide layer is formed as a protecting layer on the surface of the integrated circuit, connecting lines of a conductor, such as aluminum, are formed on the silicon oxide layer. In this case, in order to decrease the parasitic capacity between the epitaxial layer and the aluminum connecting lines, the above-mentioned silicon oxide layer is made thick. Furthermore, in order to prevent a so-called parasitic effect from occuring between the semiconductor elements, an isolation region between the semiconductor elements is formed by introducing impurities having an opposite conductivity type so that of the epitaxial layer into a predetermined portion of the epitaxial layer.
A semiconductor element (e.g. an npn-type bipolar transistor) of an integrated circuit is illustrated in the schematic sectional view of FIG. 1. Such a bipolar transistor is illustrated in FIG. 2 of U.S. Pat. No. 3,911,471. In FIG. 1, reference numerals 1, 2, 2' and 3 indicate a p-type silicon substrate, an n-type silicon epitaxial layer, an isolated region and an n-type buried layer, respectively. The electrical resistance of the epitaxial layer 2 is high and, consequently, the breakdown voltage between the collector and the base of the bipolar transistor is high. The buried layer 3 can reduce the series resistance of the collector. Reference numerals 4, 5, 6 and 7 indicate a p-type base region, an n-type emitter region, an n-type collector connecting region and an isolation region, respectively. These regions 4, 5, 6 and 7 are formed in the epitaxial layer 2. Since the isolation region 7 has the opposite conductivity type to that of the epitaxial layer and surrounds the isolated region 2', it is possible to electrically isolate the bipolar transistor from other transistors and passive elements (not shown). Reference numerals 8, 8A through 8C, 9, 10 and 11 indicate a silicon oxide layer, thick portions of the silicon oxide layer, a collector electrode, a base electrode and an emitter electrode, respectively. The thick portions 8A, 8B and 8C of the silicon oxide layer 8 decrease the parasitic capacitance between the epitaxial layer and the connecting lines of the electrodes 9, 10 and 11. According to FIG. 1 the thick portions of the silicon oxide layer are separated, but the thick portions may be combined in a manner not shown in FIG. 1.
The bipolar transistor illustrated in FIG. 1 is produced in the following manner. Referring to FIG. 2, the starting material is a p-type silicon semiconductor substrate 1. N-type impurities are introduced into a predetermined portion of the silicon substrate 1 by ion-implantation or thermal diffusion to form a buried layer 3. An n-type silicon epitaxial layer 2 is formed on the silicon substrate 1 by epitaxial growth and, at the same time, some impurities diffuse out of the buried layer 3 into the epitaxial layer 2, so that the buried layer 3 expands up to a broken line in FIG. 2. A silicon nitride layer serving as an anti-oxidation masking layer is formed on the epitaxial layer 2 by chemical vapor deposition and, then, is selectively removed by photoetching, so that portions 12A, 12B and 12C of the silicon nitride layer remain, as illustrated in FIG. 2. If desired, a thin oxide layer may be provided under the silicon nitride layer.
Next, the semiconductor body comprising the silicon substrate 1 and the silicon epitaxial layer 2 is thermally oxidized at 1000.degree. C. for approximately 2 hours. Since the silicon nitride layer portions 12A, 12B and 12C serve as an anti-oxidation mask during the oxidation period, a silicon dioxide (SiO.sub.2) layer 13 having a thickness of approximately 700 nm is formed, as illustrated in FIG. 3.
The formed silicon dioxide layer 13 is removed by etching to expose a portion of the epitaxial layer 2. Then, the semiconductor body is also thermally oxidized at 1000.degree. C. for approximately 8 hours to form a thick silicon dioxide layer 14 having a thickness of approximately 1.4 .mu.m, as illustrated in FIG. 4.
Next, a photoresist layer (not shown) is applied on the entire surface and, then, a portion of the resist layer which lies on the silicon nitride layer portion 12A is removed. P-type impurities are introduced through the silicon nitride layer portion 12A into the epitaxial layer 2 by ion-implantation to form a high concentration region 15 of p-type impurities, as illustrated in FIG. 5. After the applied resist layer is removed, another photoresist layer is applied onto the entire surface, and then, a portion of the resist layer which lies on the silicon nitride layer portion 12B is removed. N-type impurities are introduced through the silicon nitride layer portion 12B into a portion of the epitaxial layer 2 by ion-implantation to form a high concentration region 16 of n-type impurities, as illustrated in FIG. 5.
The obtained semiconductor body is heated at 1100.degree. C. for approximately 1 hour, whereby the p-type impurities in the high concentration regions 15 diffuse into the epitaxial layer 2 and arrive at the silicon substrate 1 to form an isolation region 7 for isolating semiconductor elements from each other and, at the same time, the n-type impurities in the high concentration region 16 diffuse and arrive at the buried layer 3 to form a collector connecting region 6, as illustrated in FIG. 6.
Next, the remaining silicon nitride layer portions 12A, 12B and 12C are removed to expose portions of the epitaxial layer 2. The obtained semiconductor body is thermally oxidized at 900.degree. C. for approximately 30 minutes to form a thin silicon dioxide layer 8, having a thickness of approximately 50 nm, on the surfaces of the exposed portions the epitaxial layer 2 including the isolation region 7 and the collector connecting region 6, as illustrated in FIG. 7. A patterned photo resist layer 17 is formed on the thin and thick silicon dioxide layers 8 and 14, as illustrated in FIG. 7. P-type impurities are introduced through a portion of the thin silicon dioxide layer 8 into a portion of the isolated region 2' of the epitaxial layer 2 by ion-implantation to form a high concentration region 18 of the p-type impurities.
The obtained semiconductor body is annealed by heating at 1000.degree. C. for approximately 10 minutes, whereby the impurities in the high concentration region 18 diffuse to a predetermined depth in the epitaxial layer 2, so that a base region 5 is formed, as illustrated in FIG. 8. Then, N-type impurities are introduced into a portion of the base region 5 by ion-implantation subsequent to etching of a portion of the thin silicon dioxide layer lying on the base region 5 by photoetching. An annealing treatment is carried out at 1000.degree. C. for approximately 20 minutes to form an emitter region 4, as illustrated in FIG. 1.
Openings for the collector electrode 9 and for the base electrode 11 are formed in the thin silicon dioxide layer above the collector connecting region 6 and the base region 5, respectively, by photoetching, as illustrated in FIG. 1. Finally, a conductor layer of aluminum is formed on the entire surface by vapor deposition and, then, is selectively removed by photoetching to form the collector, base and emitter electrodes 9, 11 and 10, respectively. In the above described manner, an npn-type bipolar transistor isolated from other elements is produced, as illustrated in FIG. 1.
However, when the thick silicon dioxide layer 14 (FIG. 4) is formed prior to the introduction of impurities into the epitaxial layer 2, a portion of the epitaxial layer lying under the silicon nitride layer portions 12A, 12B and 12C is oxidized into silicon dioxide. Namely, a portion of the thick silicon dioxide layer 14 enters under the silicon nitride layer portions to form a so-called bird's beak, as illustrated in FIG. 4. Since the bird's beak of silicon dioxide prevents the impurities from entering into the epitaxial layer 2, for example, in order to form the isolation region 7 having a width of 1 .mu.m, it is necessary to make the width of the silicon nitride layer portion 12A approximately 3 .mu.m. As the width of the silicon nitride layer portion 12A increases, on the one hand, its area increases, and on the other hand, the area for semiconductor elements and passive elements of the integrated circuit decreases. Therefore, it is difficult to increase the degree of integration of the semiconductor elements and the passive elements in the integrated circuit.
Furthermore, according to the above-mentioned production method, the method comprises the step of forming the thick silicon dioxide layer, and the step of diffusing the impurities for forming the isolation region and the collector connecting region, namely, a heat-treatment is carried out at least two times. When the heat-treatment is repeated, the impurities in the buried layer diffuse upward in the epitaxial layer. As the result of this, the breakdown voltage between the collector and the emitter decreases.